Flavors Technology Incorporated

Slide 5 of 24

The Parallel Inference Machine, or PIM, is based on a massively parallel architecture. Physically, a PIM system consists of one Boss board, and any combination of 1to 5 additional Processor or I/O boards. The system is commercial off-the-shelf VME-based, and the various boards are based on the Motorola PowerPC 604e chip.

The PIM is predictable and fast. Code is executed in a fixed frame time; there are no halts or interrupts in the architecture. All processing cells have guaranteed resources so that they are running on each frame, independent of whether or not they have code in them. A PIM can be incrementally scaled to meet the needs of an application by simply adding another board. This would provide an additional 500 processing cells at 60Hz with no impact on proven, running code.

The PIM features a large shared memory that is accessible by all cells. Further, each cell has its own local memory. Flash cards can be installed to snapshot the state of the PIM on each frame for deployed applications where state must be restored after a fault.

When describing the PIM execution, we refer to its cycle as systolic. In the case of a PIM running at 60Hz, every frame each cell will read from shared memory, execute its code, and write results back to shared memory, guaranteed.